Compared to the conventional trench MOSFET, the super-junction trench MOSFET are more attractive due to its higher breakdown voltage and lower specific Rds (drain-source resistance). As is known to all, the super-junction trench MOSFET is implemented by a p type column structure and an n type column structure arranged in parallel and connecting to each other onto a heavily doped substrate, however, the manufacturing yield is not stable because it is very sensitive to the fabrication processes and conditions such as: the p type column structure and the n type column structure dopant re-diffusion issue induced by subsequent thermal processes, trapped charges within the column structures, etc. . . . All that will cause a hazardous condition of charges imbalance to the super-junction trench MOSFET. More specifically, these undesired influences become more pronounced with a narrower column structure width for a lower bias voltage ranging under 200V.
U.S. Pat. No. 7,601,597 disclosed a method to avoid the aforementioned p type column structure and the n type structure dopant re-diffusion issue, for example in an N-channel trench MOSFET, by setting up the p type column formation process at a last step after all diffusion processes such as: sacrificial oxidation after trench etch, gate oxidation, P body region formation and n+ source region formation, etc. . . . have been finished. The disclosed super-junction trench MOSFET is shown in FIG. 1A.
However, the disclosed method is not cost effective because that, first, the p type column structure is formed by growing an additional p type epitaxial layer after etching deep trenches; second, an additional CMP (Chemical Mechanical Polishing) is required for surface planarization after the p type epitaxial layer is grown; third, double trench etches are necessary (one for shallow trenches for trenched gates formation and another for the deep trenches for the p type column structure formation), all the increased cost is not conductive to mass production. Moreover, other factors such as: the charges imbalance caused by the trapped charges within the column structures is still not resolved.
Prior arts (paper “Industrialization of Resurf Stepped Oxide Technology for Power Transistors”, by M. A. Gajda, etc., and paper “Tunable Oxide-Bypassed Trench Gate MOSFET Breaking the Ideal Super-junction MOSFET Performance Line at Equal Column Width”, by Xin Yang, etc.) disclosed device structures in order to resolve the limitation caused by the conventional super-junction trench MOSFET discussed above, as shown in FIG. 1B and FIG. 1C. Except for different terminologies (the device structure in FIG. 1B named with RSO: Resurf Stepped Oxide and the device structure in FIG. 1V named with TOB: Tunable Oxide-Bypassed), both device structures in FIG. 1B and FIG. 1C are basically the same which can achieve a lower specific Rds and a higher breakdown voltage than the conventional super-junction trench MOSFET because the epitaxial layer (epi, as illustrated in FIG. 1B and FIG. 1C) has a higher doping concentration than the conventional super-junction trench MOSFET.
Refer to FIG. 1B and FIG. 1C again, both the device structures have a deep trench with a thick oxide layer along trench sidewalls and bottom into a drift region. Only difference is that, the device structure in FIG. 1B has a single epitaxial layer (N epi, as illustrated in FIG. 1B) while the device structure in FIG. 1C has double epitaxial layers (Epi1 and Epi2, as illustrated in FIG. 1C, Epi1 supported on a heavily doped substrate has a lower doping concentration than Epi2 near a channel region). Due to the p type column structure and the n type column structure interdiffusion, both the device structures in FIG. 1B and FIG. 1C do not have charges imbalance issue, resolving the technical limitation caused by the conventional super-junction trench MOSFET, however, the benefit of both the device structures in FIG. 1B and FIG. 1C over the conventional super-junction trench MOSFET only pronounces at the bias voltage ranging under 200V, which means that, the conventional super-junction trench MOSFET has a lower Rds when the bias voltage is beyond 200V.
Therefore, there is still a need in the art of the semiconductor power device, particularly for super-junction trench MOSFET design and fabrication, to provide a novel cell structure, device configuration and fabrication process that would resolve these difficulties and design limitations.